User contributions for Lidnariq

10 April 2023

• 01:4701:47, 10 April 2023 diff hist +37‎ Casio PV-1000/ASIC registers ‎ not an "Uncommitted Logic Array"
• 01:4401:44, 10 April 2023 diff hist +21‎ Casio PV-1000 ‎ not an Uncommited Logic Array, but a sea of MOSFETs...
• 00:2400:24, 10 April 2023 diff hist +93‎ Casio PV-1000/ASIC registers ‎ →‎Square 1 ($F8) > write: more of plgDavid's findings
• 00:2100:21, 10 April 2023 diff hist +6‎ Casio PV-1000/ASIC registers ‎ →‎Sound control ($FB) > write
• 00:2100:21, 10 April 2023 diff hist +183‎ Casio PV-1000/ASIC registers ‎ →‎Sound control ($FB) > write: update with plgDavid's research

7 April 2023

• 19:0219:02, 7 April 2023 diff hist +1‎ Casio PV-1000/ASIC pinout ‎ continuity tests. Pretty certain 59+58+26+27 are the "real" power supply pins

6 April 2023

• 23:0823:08, 6 April 2023 diff hist +358‎ Casio PV-1000/ASIC registers ‎ port FB is some kind of sound control
• 22:0022:00, 6 April 2023 diff hist +26‎ Casio PV-1000/ASIC registers ‎ →‎Display properties ($FF) > write: indeed, display disable
• 05:2205:22, 6 April 2023 diff hist −1‎ m Casio PV-1000/Controller port pinout ‎ numerical agreement typo
• 04:2904:29, 6 April 2023 diff hist 0‎ m Casio PV-1000/Cartridge connector ‎ typo

5 April 2023

• 04:5404:54, 5 April 2023 diff hist 0‎ m Casio PV-1000/ASIC registers ‎ →‎Display properties ($FF) > write: typo
• 04:5404:54, 5 April 2023 diff hist +15‎ m Casio PV-1000/ASIC registers ‎ →‎Display properties ($FF) > write: more clear
• 03:1203:12, 5 April 2023 diff hist +18‎ Casio PV-1000/ASIC registers ‎ →‎Display properties ($FF) > write: pattern RAM address moveable
• 03:0603:06, 5 April 2023 diff hist 0‎ Casio PV-1000/ASIC pinout ‎ typo
• 02:5402:54, 5 April 2023 diff hist +977‎ N Casio PV-1000/Video ‎ Created page with "The PV-1000's video timing divides a frame into 288 pixels horizontally by 262 scanlines. The pixel clock is the crystal divided by 4, or roughly 4.47MHz. This corresponds to an exact pixel aspect ratio of 48:35, or approximately 4:3. This makes the horizontal sync rate the quite-slow 15536Hz and the vertical sync rate the almost-normal 59.299Hz Of those 288 pixels, 224 contain actual video content. These 224 pixels are already significantly wider than the majority of c..."
• 02:3302:33, 5 April 2023 diff hist +2,235‎ N Casio PV-1000/Controller ‎ Created page with "The Casio PV-1000 Joystick is a 2-axis, 4-button joystick. Pictures are available here: https://commons.wikimedia.org/wiki/Category:Casio_PV-1000_accessories Reading its status is much like one how one reads the buttons on a Game Boy. == Input (port $FD write) == 7 bit 0 ---- ---- xxxx ABCD |||| |||+-- 1: include information about joysticks' "Attack" buttons ||+--- 1: include information about joysticks' up and left directions |+---- 1: in..."
• 01:3401:34, 5 April 2023 diff hist +3,015‎ N Casio PV-1000/ASIC pinout ‎ Created page with " /^\ / \ / \ VCC -- / 1 64 \ ?? ?? ?? ?? / 2 63 \ <- GPI63 Red <- / 3 62 \ <- GPI62 Green <- / 4 61 \ <- GPI61 Blue <- / 5 60 \ <- GPI60 /CSync <- / 6..."

4 April 2023

• 00:2900:29, 4 April 2023 diff hist −21‎ Casio PV-1000/Cartridge connector ‎No edit summary
• 00:2400:24, 4 April 2023 diff hist +140‎ Casio PV-1000/ASIC registers ‎ →‎Tilemap address ($FE) > write: new test result

3 April 2023

• 21:3521:35, 3 April 2023 diff hist +610‎ Casio PV-1000 ‎No edit summary
• 06:0306:03, 3 April 2023 diff hist +2,720‎ N Casio PV-1000/ASIC registers ‎ Created page with "The µPD65010G031 ULA has 10 total ports. They are fully decoded, available via Z80 I/O instructions at $F8-$FF. There are eight write-only functions and two read-only functions. === Square 1 ($F8) > write === 7 bit 0 ..PP PPPP || |||| ++-++++--- Period for first square wave. f_square = f_ULA ÷ 1024 ÷ (63-P) ≈ 8739 Hz ÷ (63-P) Where f_ULA is the 17.897727MHz crystal divided by 2. If P is specified to be 63, it instead si..."
• 04:2704:27, 3 April 2023 diff hist +588‎ N Casio PV-1000/Controller port pinout ‎ Created page with "The TJ-1 controllers used by Casio's PV-1000 and PV-2000 uses a Mini-DIN-8. The game expects the controllers to form a 4x4 button matrix, manually scanned by the software. GPI2 ___|___ GND ---8/-O O O-\6--- GPO52 / \ GPO55 ---5|-O O O-|3--- GPO53 \ | / GPI1 ---2]-O | O-[1--- n/c ---|--- | GPO54 The actual mapping of which General Purpose Outp..."
• 04:1704:17, 3 April 2023 diff hist +80‎ m Casio PV-1000/Cartridge connector ‎No edit summary
• 04:1504:15, 3 April 2023 diff hist +1,053‎ N Casio PV-1000/Cartridge connector ‎ Created page with "This diagram represents a top-down looking directly into the connector. The "B" side pins are on the label side of the cartridge. Pin pitch is assumed to be 0.1 inch, but this has not yet been verified. Cartridges are required to have a key cut between 10 and 11. (front) (back) PV-1000 | Cart | PV-1000 ------- +5V -- |B01 A01| -- GND /IRQ -> |B02 A02| -- chassis ground A14 -> |B03 A03| <- A15 A12 -..."
• 04:0604:06, 3 April 2023 diff hist +273‎ N Casio PV-1000 ‎ create a stub