Casio PV-1000/ASIC registers: Difference between revisions
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(Created page with "The µPD65010G031 ULA has 10 total ports. They are fully decoded, available via Z80 I/O instructions at $F8-$FF. There are eight write-only functions and two read-only functions. === Square 1 ($F8) > write === 7 bit 0 ..PP PPPP || |||| ++-++++--- Period for first square wave. f<sub>square</sub> = f<sub>ULA</sub> ÷ 1024 ÷ (63-P) ≈ 8739 Hz ÷ (63-P) Where f<sub>ULA</sub> is the 17.897727MHz crystal divided by 2. If P is specified to be 63, it instead si...") |
(→Tilemap address ($FE) > write: new test result) |
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+---------- Always 1. (Probably pulled up by resistor next to Z80) | +---------- Always 1. (Probably pulled up by resistor next to Z80) | ||
=== Tilemap address ($FE) > write === | === Tilemap and pattern RAM address ($FE) > write === | ||
7 bit 0 | 7 bit 0 | ||
BBBB AA.. | |||
|||| || | |||| || | ||
++++-++---- Address A15-A10 from where to fetch the tilemap. | ++++-++---- Address A15-A10 from where to fetch the tilemap. | ||
|||| Almost all software write $B8, meaning the ULA fetches tilemap from $B802 through $BAFD. | |||
++++------- Address A15-A12 from where to fetch pattern RAM tiles (A11-A10 always 1) | |||
The common value of $B8 means that ULA fetches data for tiles $E0-$FF from $BC08-$BFFF | |||
=== Display properties ($FF) > write === | === Display properties ($FF) > write === | ||
Revision as of 00:24, 4 April 2023
The µPD65010G031 ULA has 10 total ports. They are fully decoded, available via Z80 I/O instructions at $F8-$FF.
There are eight write-only functions and two read-only functions.
Square 1 ($F8) > write
7 bit 0 ..PP PPPP || |||| ++-++++--- Period for first square wave.
fsquare = fULA ÷ 1024 ÷ (63-P) ≈ 8739 Hz ÷ (63-P)
Where fULA is the 17.897727MHz crystal divided by 2.
If P is specified to be 63, it instead silences the square wave.
Square 2 ($F9) > write
Same as Square 1, but 3dB louder.
Square 3 ($FA) > write
Same as Square 1, but 6dB louder.
Unknown ($FB) > write
Existing games write 0, 2, or 3.
Interrupt controller? ($FC) > write
Existing games write 0, 1, or 3.
Interrupt status? ($FC) < read
7 bit 0 ZAAA AABC |||| |||| |||| |||+-- Unclear. Counts 2 scanlines? |||| ||+--- Usually 1? |+++-++---- Always 0? +---------- Always 1 (Probably pulled up by resistor next to Z80)
GPO ($FD) > write
7 bit 0 .AAA BBBB ||| |||| ||| ++++-- 4 general purpose outputs, accessible via both controller ports +++------- Strongly implied to exist on the ULA, but not accessible externally
GPI ($FD) < read
7 bit 0 ZAAA BBCC |||| |||| |||| ||++-- 2 general purpose inputs for reading the player 1 joystick |||| ++---- 2 general purpose inputs for reading the player 2 joystick |+++------- Always 0. (Strongly implied to exist on the ULA, but grounded there) +---------- Always 1. (Probably pulled up by resistor next to Z80)
Tilemap and pattern RAM address ($FE) > write
7 bit 0
BBBB AA..
|||| ||
++++-++---- Address A15-A10 from where to fetch the tilemap.
|||| Almost all software write $B8, meaning the ULA fetches tilemap from $B802 through $BAFD.
++++------- Address A15-A12 from where to fetch pattern RAM tiles (A11-A10 always 1)
The common value of $B8 means that ULA fetches data for tiles $E0-$FF from $BC08-$BFFF
Display properties ($FF) > write
7 bit 0
AAAB CDDD
|||| ||||
|||| |+++-- Border color. (0=black, 1=red, 2=green, 3=yellow, 4=blue, &c).
|||| +----- Display disable? (faster Z80?)
|||+------- Pattern RAM disable
||| (0: Tiles $E0-$FF are fetched from $BC08-$BFFF
||| 1: Tiles $E0-$FF are fetched from normal address)
+++-------- Address A15-A13 from where to fetch patterns
(0: Patterns are fetched from $0008-$1BFF or -$1FFF
1: starting at $2008
2: starting at $4008 &c
It's not yet confirmed that the pattern fetch is a full three bits wide. At least Dig Dug uses both B and the lsbit of AAA.
Other sources (e.g. Enri refer to the pattern memory as "PCG")
