Casio PV-1000/Rendering: Revision history

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3 June 2023

2 June 2023

25 May 2023

  • curprev 02:4102:41, 25 May 2023‎ Lidnariq talk contribs‎ m 1,333 bytes 0‎ No edit summary
  • curprev 02:4102:41, 25 May 2023‎ Lidnariq talk contribs‎ 1,333 bytes +1,333‎ Created page with "There are 288 pixels on each scanline. Note that pixel 0 is defined as the start of hsync. During each of the 192 active scanlines, if enabled in the configuration register, the ASIC does the following: BUSREQ is asserted from pixels 20 through 267; the other 40 pixels it's deasserted. The first two pixels are during hsync. While the Z80 asserts BUSACK # the ASIC continuously asserts /MREQ # the ASIC runs the same 8 pixel 4 fetch pattern: TilemapEntry Bitplane Bitpl..."
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