Casio PV-1000/ASIC pinout

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< Casio PV-1000
Revision as of 06:48, 4 June 2023 by Lidnariq (talk | contribs) (believed GPO mapping)
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                                        /^\
                                       /   \
                                      /     \
                              VCC -- / 1  64 \ ?? ??
                              ?? ?? / 2    63 \ <- GPI63 / rpFDd0
                            Red <- / 3      62 \ <- GPI62 / rpFDd1
                         Green <- / 4        61 \ <- GPI61 / rpFDd2
                         Blue <- / 5          60 \ <- GPI60 / rpFDd3
                      /CSync <- / 6            59 \ -- Gnd
                /Colorburst <- / 7              58 \ -- VCC
                 square$FA <- / 8                57 \ ?? Gnd / ?rpFDd4?
                square$F9 <- / 9                  56 \ ?? Gnd / ?rpFDd5?
               square$F8 <- / 10                   55 \ -> GPO55 / wpFDq0
                    Gnd ?? / 11              ( )    54 \ -> GPO54 / wpFDq1
                  9MHz -> / 12                       53 \ -> GPO53 / wpFDq2
               /BUSRQ <- / 13                         52 \ -> GPO52 / wpFDq3
             /BUSACK -> / 14                          51 / ?? ?wpFDq4?
                /WR -> / 15                          50 / ?? ?wpFDq5?
               /RD <> / 16                          49 / ?? ??                Orientation:
            /IORQ -> / 17                          48 / -> /RAMCE             |          |
           /MREQ <> / 18                          47 / ?? ??                 .------------.
           /INT <- / 19                          46 / <? /RESET           52-|  NEC JAPAN |-32
             D7 <> \ 20                         45 / <> A0                   | D65010G031 |
              D6 <> \ 21    ( )                44 / <> A1                    |O          O|
               D5 <> \ 22                     43 / <> A2                     |            |
                D4 <> \ 23                   42 / <> A3                   64-|   8337P5   |-20
                 D3 <> \ 24                 41 / <> A4                       '------------'
                  D2 <> \ 25               40 / <> A5                         |          |
                  VCC -- \ 26             39 / <> A6                          1          19
                   Gnd -- \ 27           38 / <> A7
                     D1 <> \ 28         37 / <> A8              Legend:
                      D0 <> \ 29       36 / <> A9               ------------------------------
                      A15 <> \ 30     35 / <> A10               --[chip]-- Power
                       A14 <> \ 31   34 / <> A11                ->[chip]<- Input
                        A13 <> \ 32 33 / <> A12                 <-[chip]-> Output
                                \     /                         <>[chip]<> Bidirectional
                                 \   /                          ??[chip]?? Unknown
                                  \ /
                                   V


By context on the PCB, it is implied that pins 51 and 50 are additional GPOs, but they were cut during rework. Similarly, it is implied that some of pins 59, 57, 56 could be additional GPIs.

"rpFDdN" means "read from port FD, bit N" "wpFDqN" means "write to port FD, bit N"